EPLD - Altera EPLD Series Device Family of Non-Volatile EPROMs.

EPLD - Altera EPLD Series Device Family of Non-Volatile EPROMs. Simple Type:...

Altera EPLD Series Device Family of Non-Volatile EPROMs. Simple Type: Integrated Circuit (IC)

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100% generically tested to provide 100% programming yield
24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages
Additional design entry and simulation support provided by EDIF, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence
Complete device family with logic densities of 300 to 900 usable gates
Device erasure and reprogramming with non-volatile EPROM configuration elements
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz
Programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls
Programmable security bit for protection of proprietary designs
Programming support with Altera’s Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors
Software design support featuring the Altera MAX+PLUS II development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-part